1. Field of the Invention
The present invention relates to the fabricating of a semiconductor device. More particularly, the present invention relates to a method of filling a trench in a semiconductor substrate, and to a method of forming an isolating layer structure which defines an active region and a field region of a semiconductor substrate.
2. Description of the Related Art
Semiconductor devices constitute the main electronic components, such as transistors and diodes, of today's electronic devices. Also, the array of electronic devices, such as personal computers, in wide-spread use is constantly increasing. For each of its new applications, an electronic device must often store greater and greater quantities of electronic data and process data at higher and higher speeds. Accordingly, semiconductor devices are being developed with an aim towards improving the degree to which they are integrated, their reliability, and their-responsiveness (operating speed).
To these ends, electrically isolating electronic components on a semiconductor substrate has taken on a greater importance in the fabricating of an integrated semiconductor device. Also, the forming of the structure that will electrically isolate the various electronic components, i.e., the forming of an “isolation” structure, is usually the first of several main processes in the fabricating of an integrated semiconductor device. Therefore, the process used for forming the isolation structure can significantly affect the size of the device and process margins of subsequent processes.
Generally, an isolation layer is the most widely used structure for isolating electronic components on a substrate, due to the fact that it may be produced by a simple process. For example, an isolation layer may be formed by a thermal field oxidation process such as a local oxidation of silicon (LOCOS) process. According to the LOCOS process, an oxide layer and a nitride layer are sequentially formed on a silicon substrate. The nitride layer is then patterned. Next, the silicon substrate is selectively oxidized using the patterned nitride layer as a mask to form a field oxide layer. The non-oxidized portions of the substrate left between respective portions of the field oxide layer become the active region of the substrate on which electronic components are subsequently formed.
However, oxygen may infiltrate into the sides of the oxide layer under the mask (patterned nitride layer) while the silicon substrate is being oxidized. As a result, a so-called bird's beak is formed at each side of the field oxide layer. The bird's beak extends the field oxide layer into an active region. That is, the size of the active region is in effect reduced. Hence, electrical characteristics of the semiconductor device are degraded.
Therefore, a shallow trench isolation (STI) process has been used as an alternative to the LOCOS process to form an isolation structure. According to the STI process, first, a silicon substrate is etched to form a trench. An oxide layer is then formed on the silicon substrate to such a thickness as to overfill the trench. Finally, the oxide layer is etched or polished (planarized) by an etch-back process or a chemical mechanical polishing (CMP) process until the upper surface of the substrate is exposed. The portion of the oxide layer left in the trench constitutes a field oxide layer.
However, the active region and field region are becoming smaller as the degree to which semiconductor devices become integrated increases. Thus, the trenches used for forming the isolation structure are becoming narrower and deeper. Likewise, the aspect ratio of the trenches (the ratio of the depth to width of the trench) is increasing. Accordingly, it is becoming increasingly difficult to fill such trenches with an oxide layer without voids or a seam being produced in the layer.
In view of such potential problems and difficulties, a high density plasma enhanced chemical vapor deposition (HDP-CVD) process has been employed for filling relatively narrow trenches with an oxide having a good gap filling characteristic. Examples of such an oxide include O3-tetra ethyl ortho silicate (O3-TEOS) and undoped silicate glass (USG). However; O3-TEOS or USG deposited by HDP-CVD may build up excessively at the entrance of the trench such that the final oxide layer does not fill the trench completely. Furthermore, a seam may be produced in a portion of the oxide layer which protrudes from the trench as will be described below with respect to FIGS. 1A-1D which illustrate a conventional method of forming an isolation layer.
Referring to FIG. 1A, a pad oxide layer 12 is formed on a semiconductor substrate 10 by a thermal oxidation process. A nitride layer (not shown) is then formed on the pad oxide layer 12. The nitride layer is patterned to form a pad nitride layer pattern 14.
Referring to FIG. 1B, the pad oxide layer 12 and the semiconductor substrate 10 may are etched using the pad nitride layer pattern 14 as an etch mask to form a trench 16. A liner oxide layer 18 is then formed along the substrate 10 within the trench 16 by a thermal oxidation process.
Referring to FIG. 1C, silicon oxide is deposited on the sides and bottom of the trench 16 and an upper surface of the pad nitride layer pattern 14 to form a silicon oxide layer 20 by an HDP-CVD process. Reaction gases of the HDP-CVD process may include a mixture of silicon nitride (SiN4) gas and oxygen (O2). Furthermore, the plasma source gas of the HDP-CVD process may be helium (He).
However, as the silicon oxide layer 20 is being formed, the silicon oxide on upper portions of the sides of the trench 16 may be sputtered due to the nature of the HDP-CVD process. The sputtered silicon oxide adheres to the silicon oxide already deposited at the side of the trench 16 opposite that from which the silicon oxide is sputtered. As a result, an overhang “A” is produced in the silicon oxide layer 20. The overhang “A” hangs over the remaining unfilled portion of the trench 16 forming a neck in the unfilled portion of the trench where the upper part of the unfilled portion of the trench is narrower than the lower part of the unfilled portion of the trench.
Referring to FIG. 1D, the silicon oxide layer 20 may be planarized by a CMP process until an upper surface of the pad nitride layer pattern 14 is exposed. The pad nitride layer pattern 14 and the pad oxide layer 12 are then removed to form an isolation layer 22 having an upper surface disposed above that of the semiconductor substrate 10. However, as shown in the figure, voids or seams V may be produced in the isolation layer 22 due to the overhang.
In order to prevent such voids or seams from being formed, the silicon oxide layer is etched (wet- or dry-etched) in an attempt to remove any overhang and thereby expand the entrance of the trench before the trench is filled. The trench is subsequently filled with additional silicon oxide. However, the etching process for expanding the entrance of the trench may still not provide the remaining trench with a sufficiently wide entrance which allows for the trench to be filled completely. Furthermore, in the case in which the etching process for expanding the entrance of the trench is a dry etching process, the pad oxide layer may be over-etched or damaged by the plasma used in the dry etching process.